Nonvolatile memory devices can retain data stored therein even when power thereto is interrupted. Some nonvolatile memory devices employ flash memory cells having stacked gate structures. Each of the stacked gate structures can include a tunnel oxide layer, a floating gate, an inter-gate dielectric layer and a control gate electrode, which can be sequentially stacked on a channel region. The reliability and program efficiency of the flash memory cell may be improved by improving the film quality of the tunnel oxide layer and increasing the coupling ratio of the cells.
Phase changeable memory devices are also known. FIG. 1 is an equivalent circuit of a typical phase changeable memory cell. Referring to FIG. 1, the phase changeable memory cell can include an access transistor TA and a variable resistor C, which are serially connected to each other. The variable resistor C can provide a data storage element that includes a bottom electrode, a top electrode and a phase changeable material layer interposed between the bottom electrode and the top electrode. The top electrode of the variable resistor C is connected to a plate electrode PL. The access transistor TA includes a source region connected to the bottom electrode, a drain region spaced apart from the source region and a gate electrode located over a channel region between the source and drain regions. The gate electrode and the drain region are electrically connected to a word line WL and a bit line BL, respectively. As a result, an equivalent circuit of the phase changeable memory cell may include elements/components that are similar to those included in some dynamic random access memory (DRAM) cells. However, a property of the phase changeable material layer is different from that of a dielectric layer which is sometimes included in capacitors of DRAM cells. That is to say, the phase changeable material layer exhibits two stable states according to a temperature.
FIG. 2 is a graph that illustrates a property of the phase changeable material layer. The abscissa represents time T and the ordinate represents temperature TMP applied to the phase changeable material layer. Referring to FIG. 2, if the phase changeable material layer is heated to a temperature that is greater than the melting point Tm for a first duration T1 and cooled down rapidly, the phase changeable material layer is transformed into an amorphous state (refer to curve {circle around (1)}).
Alternatively, if the phase changeable material layer is heated to a temperature that is in the range between the crystallization temperature Tc of the phase changeable material and the melting temperature Tm for a second duration T2 (greater than the first duration T1) and is cooled down, the phase changeable material layer is transformed into a crystalline state (refer to curve {circle around (2)}). The resistivity of the phase changeable material layer having the amorphous state is greater than that of the phase changeable material layer in the crystalline state. Thus, it is possible to determine whether the information stored in the memory cell is a logic “1” or a logic “0” by detecting the current that flows through the phase changeable material layer in a read mode. A compound material layer containing germanium (Ge), stibium (Sb) and tellurium (Te) (hereinafter, referred to as a GST layer) is widely used as the phase changeable material layer.
FIG. 3 is a cross sectional view illustrating a data storage element of conventional phase changeable memory device. Referring to FIG. 3, a conventional phase changeable memory includes an interlayer dielectric layer 14 on a semiconductor substrate (not shown) having a contact plug 16 and a bottom electrode 12 therein. The contact plug 16 extends through the interlayer dielectric layer 14 so as to contact the bottom electrode 12. A phase changeable layer 18 is on the contact plug 16 and the interlayer dielectric layer 14. An upper electrode 20 is on the phase changeable layer 18.
Because the phase changeable layer 18 is on the contact plug 16, a normal profile of the contact between the phase changeable layer 18 and the contact plug 16 can extend in a vertical direction. When heat is generated by the contact resistance at a contact portion between the contact plug 16 and the phase changeable layer 18, the central region 22 of the contact portion may remain at a high temperature. However, an edge region A of the contact portion may be maintained lower than a temperature necessary to change the phase of the phase changeable layer 18 due to, for example, heat leakage into the interlayer dielectric layer 14 around the contact portion. This may result in the generation of abnormal regions A where the respective phase of the region is not fully changed to an amorphous state. Such abnormal regions A may commonly be found at the edge of the contact portion, where charge leakage e can occur. Such charge leakage may lead to errors in the retention of data within the phase changeable memory cell.